Espressif WiFi Module Agent Espressif Device Esp32 Esp8685 Datasheet

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Espressif WIFI module agent espressif device esp32 ESP8685 Datasheet
ESP8685
Datasheet

Ultra­Low­Power SoC with RISC­V Single­Core CPU
Supporting IEEE 802.11b/g/n (2.4 GHz Wi­Fi) and Bluetooth 5 (LE) 2 MB flash embedded in the 4×4 mm QFN package

ESP8685 is an ultra-low-power and highly-integrated MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It has:

•A complete Wi-Fi subsystem that complies with IEEE 802.11b/g/n protocol and supports Station mode, SoftAP mode, SoftAP + Station mode, and promiscuous mode
•A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth mesh
•State-of-the-art power and RF performance
•32-bit RISC-V single-core processor with a four-stage pipeline that operates at up to 160 MHz
•400 KB of SRAM (16 KB for cache) and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad

SPI, and QPI interfaces that allow connection to external flash
•Reliable security features ensured by
-Cryptographic hardware accelerators that support AES-128/256, Hash, RSA, HMAC, digital signature and secure boot
-Random number generator
-Permission control on accessing internal memory, external memory, and peripherals
-External memory encryption and decryption
•Rich set of peripheral interfaces and GPIOs, ideal for various scenarios and complex applications

Features
Wi­Fi

•IEEE 802.11 b/g/n-compliant
•Supports 20 MHz, 40 MHz bandwidth in 2.4 GHz band
•1T1R mode with data rate up to 150 Mbps
•Wi-Fi Multimedia (WMM)
•TX/RX A-MPDU, TX/RX A-MSDU
•Immediate Block ACK
•Fragmentation and defragmentation
•Transmit opportunity (TXOP)
•Automatic Beacon monitoring (hardware TSF)
•4 × virtual Wi-Fi interfaces
•Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode
Note that when ESP8685 scans in Station mode, the SoftAP channel will change along with the Station channel
•Antenna diversity
•802.11mc FTM

Bluetooth

•Bluetooth LE: Bluetooth 5, Bluetooth mesh
•Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
•Advertising extensions
•Multiple advertisement sets
•Channel selection algorithm #2

CPU and Memory

•32-bit RISC-V single-core processor, up to 160 MHz
•384 KB ROM
•400 KB SRAM (16 KB for cache)
•8 KB SRAM in RTC
•2 MB embedded flash
•SPI, Dual SPI, Quad SPI, and QPI interfaces that



allow connection to multiple external flash


Advanced Peripheral Interfaces

•15 × programmable GPIOs
•Digital interfaces:
-3 × SPI (SPI0 and SPI1 are used to connect the embedded flash. Only SPI2 is available)
-2 × UART
- 1 × I2C
-  1 × I2S
-Remote control peripheral, with 2 transmit channels and 2 receive channels
-LED PWM controller, with up to 6 channels
-Full-speed USB Serial/JTAG controller
-General DMA controller (GDMA), with 3 transmit channels and 3 receive channels
-1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0)
•Analog interfaces:
-2 × 12-bit SAR ADCs, up to 6 channels
-1 × temperature sensor
•Timers:
-2 × 54-bit general-purpose timers
-3 × watchdog timers
-1 × 52-bit system timer

Low Power Management

•Power Management Unit with four power modes


Security

•Secure boot
•Flash encryption
•4096-bit OTP, up to 1792 bits for use
•Cryptographic hardware acceleration:
- AES-128/256 (FIPS PUB 197)

•Permission Control
•SHA Accelerator (FIPS PUB 180-4)
•RSA Accelerator
•
Random Number Generator (RNG)
•HMAC
•Digital signature


Applications (A Non­exhaustive List)
With ultra-low power consumption, ESP8685 is an ideal choice for IoT devices in the following areas:

•Smart Home
-Light control
-Smart button
-Smart plug
-Indoor positioning
•Industrial Automation
-Industrial robot
-Mesh network
-Human machine interface (HMI)
-Industrial field bus
•Health Care
-Health monitor
-Baby monitor
•Consumer Electronics
-Smart watch and bracelet
-Over-the-top (OTT) devices
-Wi-Fi and Bluetooth speaker
-Logger toys and proximity sensing toys
•Smart Agriculture
-Smart greenhouse
-Smart irrigation
-Agriculture robot
•Retail and Catering
-POS machines
-Service robot
•Audio Device
-Internet music players
-Live streaming devices
-Internet radio players
•Generic Low-power IoT Sensor Hubs
•Generic Low-power IoT Data Loggers

1.2Pin Description

Table 1: Pin Description
 

1.3Power Scheme
Digital pins of ESP8685 are divided into two different power domains:
•VDD3P3_CPU
•VDD3P3_RTC
VDD3P3_CPU is the input power supply for CPU.
VDD3P3_RTC is the input power supply for RTC analog domain and CPU. 

1.4Strapping Pins
ESP8685 has three strapping pins:
•GPIO2
•GPIO8
•GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG register.
During the chip's system reset, the latches of the strapping pins sample the voltage level as strapping bits of "0" or "1", and hold these bits until the chip is powered down or shut down.
Types of system reset include:
•power-on reset
•RTC watchdog reset
•brownout reset
•analog super watchdog reset
•crystal clock glitch detection reset
By default, GPIO9 is connected to the internal pull-up resistor. If GPIO9 is not connected or connected to an external high-impedance circuit, the latched bit value will be "1"
To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host MCU's GPIOs to control the voltage level of these pins when powering on ESP8685.
After reset, the strapping pins work as normal-function pins. Table 3 lists detailed booting configurations of the strapping pins.
Table 3: Strapping Pins
  
2.Functional Description
This chapter describes the functions of ESP8685.


2.1CPU and Memory
2.1.1CPU
ESP8685 has a low-power 32-bit RISC-V single-core microprocessor with the following features:
•four-stage pipeline that supports a clock frequency of up to 160 MHz
•RV32IMC ISA
•32-bit multiplier and 32-bit divider
•up to 32 vectored interrupts at seven priority levels
•up to 8 hardware breakpoints/watchpoints
•up to 16 PMP regions
•JTAG for debugging

2.1.2Internal Memory
ESP8685's internal memory includes:
•384 KB of ROM: for booting and core functions.
•400 KB of on­chip SRAM: for data and instructions. Of the 400 KB SRAM, 16 KB is configured for cache.
•RTC FAST memory: 8 KB of SRAM that can be accessed by the main CPU. It can retain data in Deep-sleep mode.
•4 Kbit of eFuse: 1792 bits are reserved for your data, such as encryption key and device ID.
•2 MB embedded flash

2.1.3External Flash
ESP8685 supports SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to multiple external flash.
CPU's instruction memory space and read-only data memory space can map into external flash of ESP8685, whose size can be 16 MB at most. ESP8685 supports hardware encryption/decryption based on XTS-AES to protect developers' programs and data in flash.
Through high-speed caches, ESP8685 can support at a time up to:
•8 MB of instruction memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported.
•8 MB of data memory space which can map into flash as individual blocks of 64 KB. 8-bit, 16-bit and 32-bit reads are supported.

2.1.5Cache
ESP8685 has an eight-way set associative cache. This cache is read-only and has the following features:
•size: 16 KB
•block size: 32 bytes
•pre-load function
•lock function
•critical word first and early restart

2.2System Clocks
2.2.1CPU Clock
The CPU clock has three possible sources:
•external main crystal clock
•fast RC oscillator (typically about 17.5 MHz, and adjustable)
•PLL clock
The application can select the clock source from the three clocks above. The selected clock source drives the CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock source would be the external main crystal clock divided by 2.

2.2.2RTC Clock
The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has three possible sources:
•external low-speed (32 kHz) crystal clock
•internal slow RC oscillator (typically about 136 kHz, and adjustable)
•internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256) The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:
•external main crystal clock divided by 2
•internal fast RC oscillator (typically about 17.5 MHz, and adjustable)


2.3Analog Peripherals
2.3.1Analog­to­Digital Converter (ADC)
ESP8685 integrates two 12-bit SAR ADCs.
•ADC1 supports measurements on 5 channels, and is factory-calibrated.
•ADC2 supports measurements on 1 channel, and is not factory-calibrated. For ADC characteristics, please refer to Table 12.
2.3.2Temperature Sensor
The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value.
The temperature sensor has a range of -40 °C to 125 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O load. Generally, the chip's internal temperature is higher than the operating ambient temperature.

2.4Digital Peripherals
2.4.1General Purpose Input / Output Interface (GPIO)
ESP8685 has 15 GPIO pins which can be assigned various functions by configuring corresponding registers. Besides digital signals, some GPIOs can be also used for analog functions, such as ADC.

All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are configured as an input, the input value can be read by software through the register. Input GPIOs can also be set to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as the UART, etc. For low-power operations, the GPIOs can be set to holding state.
The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while peripheral output signals can be configured to any IO pins.
Table 5 shows the IO MUX functions of each pin.
 
Reset
The default configuration of each pin after reset:
•0 - input disabled, in high impedance state (IE = 0)
•1 - input enabled, in high impedance state (IE = 1)
•2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
•3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
•4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1)
•0* - input disabled, pull-up resistor enabled (IE = 0, WPU = 0, USB_WPU = 1). See details in Notes
•1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is
0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1) 1, input enabled, in high impedance state (IE = 1)
We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table 11, or enable

internal pull-up and pull-down resistors during software initialization.
Notes
•R - These pins have analog functions.
•USB - GPIO18 and GPIO19 are USB pins. The pull-up value of a USB pin is controlled by the pin's pull-up value together with USB pull-up value. If any of the two pull-up values is 1, the pin's pull-up resistor will be enabled. The pull-up resistors of USB pins are controlled by USB_SERIAL_JTAG_DP_PULLUP bit.
•G - These pins have glitches during power-up. See details in Table 6.

Table 6: Power­Up Glitches on Pins
1 Low-level glitch: the pin is at a low level during the time period; High-level glitch: the pin is at a high level during the time period; Pull-up glitch: the pin is pulled up during the time period;
Pull-down glitch: the pin is pulled down during the time period.

Table 7 shows the peripheral input/output signals via GPIO matrix.
Please pay attention to the configuration of the bit GPIO_FUNCn_OEN_SEL:
•GPIO_FUNCn_OEN_SEL = 1: the output enable is controlled by the corresponding bit n of GPIO_ENABLE_REG:
-GPIO_ENABLE_REG = 0: output is disabled;
-GPIO_ENABLE_REG = 1: output is enabled;
•GPIO_FUNCn_OEN_SEL = 0: use the output enable signal from peripheral, for example SPIQ_oe in the column "Output enable signal when GPIO_FUNCn_OEN_SEL = 0" of Table 7. Note that the signals such as SPIQ_oe can be 1 (1'd1) or 0 (1'd0), depending on the configuration of corresponding peripherals. If it is 1'd1 in the "Output enable signal when GPIO_FUNCn_OEN_SEL = 0", it indicates that once the register GPIO_FUNCn_OEN_SEL is cleared, the output signal is always enabled by default.


Table 7: Peripheral Signals via GPIO Matrix
    

2.4.2Serial Peripheral Interface (SPI)
ESP8685 features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can only be configured to operate in SPI memory mode, while SPI2 can be configured to operate in both SPI memory and general-purpose SPI modes.
•SPI Memory mode
In SPI memory mode, SPI0 and SPI1 are used to connect the embedded SPI flash, while SPI2 can be used to connect external memory. Data is transferred in bytes. Up to four-line SDR reads and writes are supported. The clock frequency is configurable to a maximum of 120 MHz.
•SPI2 General­purpose SPI (GP­SPI) mode
When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master and slave modes. The host's clock frequency is configurable. Data is transferred in bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.
-In master mode, the clock frequency is 80 MHz at most, and the four modes of SPI transfer format are supported.
-In slave mode, the clock frequency is 60 MHz at most, and the four modes of SPI transfer format are also supported.

2.4.3Universal Asynchronous Receiver Transmitter (UART)
ESP8685 has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous communication (RS232 and RS485) at a speed of up to 5 Mbps. The UART controller provides hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF). Both UART interfaces connect to GDMA via UHCI0, and can be accessed by the GDMA controller or directly by the CPU.

2.4.4I2C Interface
ESP8685 has an I2C bus interface which is used for I2C master mode or slave mode, depending on your configuration. The I2C interface supports:
•standard mode (100 Kbit/s)
•fast mode (400 Kbit/s)
•up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)
•7-bit and 10-bit addressing mode
•double addressing mode
•7-bit broadcast address
You can configure instruction registers to control the I2C interface for more flexibility.

2.4.5I2S Interface
ESP8685 includes a standard I2S interface. This interface can operate as a master or a slave in full-duplex mode or half-duplex mode, and can be configured for 8-bit, 16-bit, 24-bit, or 32-bit serial communication. BCK clock frequency, from 10 kHz up to 40 MHz, is supported.
The I2S interface supports TDM PCM, TDM MSB alignment, TDM LSB alignment, TDM Phillips, and PDM TX interface. It connects to the GDMA controller.

2.4.6Remote Control Peripheral
The Remote Control Peripheral (RMT) supports two channels of infrared remote transmission and two channels of infrared remote reception. By controlling pulse waveform through software, it supports various infrared and other single wire protocols. All four channels share a 192 × 32-bit memory block to store transmit or receive waveform.

2.4.7LED PWM Controller
The LED PWM controller can generate independent digital waveform on six channels. The LED PWM controller:
•can generate digital waveform with configurable periods and duty cycle. The accuracy of duty cycle can be up to 18 bits.
•has multiple clock sources, including APB clock and external main crystal clock.
•can operate when the CPU is in Light-sleep mode.
•supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator.

2.4.8General DMA Controller
ESP8685 has a general DMA controller (GDMA) with six independent channels, i.e. three transmit channels and three receive channels. These six channels are shared by peripherals with DMA feature. The GDMA controller implements a fixed-priority scheme among these channels.
The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and memory-to-memory data transfer at a high speed. All channels can access internal RAM.
Peripherals on ESP8685 with DMA feature are SPI2, UHCI0, I2S, AES, SHA, and ADC.

2.4.9USB Serial/JTAG Controller
ESP8685 integrates a USB Serial/JTAG controller. This controller has the following features:
•USB 2.0 full speed compliant, capable of up to 12 Mbit/s transfer speed (Note that this controller does not support the faster 480 Mbit/s high-speed transfer mode)
•CDC-ACM virtual serial port and JTAG adapter functionality
•programming embedded/external flash
•CPU debugging with compact JTAG instructions
•a full-speed USB PHY integrated in the chip

2.4.10TWAI® Controller
ESP8685 has a TWAI® controller with the following features:
•compatible with ISO 11898-1 protocol (CAN Specification 2.0)
•standard frame format (11-bit ID) and extended frame format (29-bit ID)
•bit rates from 1 Kbit/s to 1 Mbit/s
•multiple modes of operation: Normal, Listen Only, and Self-Test (no acknowledgment required)
•64-byte receive FIFO

•acceptance filter (single and dual filter modes)
•error detection and handling: error counters, configurable error interrupt threshold, error code capture, arbitration lost capture

2.5Radio and Wi­Fi
ESP8685 radio consists of the following blocks:
•2.4 GHz receiver
•2.4 GHz transmitter
•bias and regulators
•balun and transmit-receive switch
•clock generator

2.5.12.4 GHz Receiver
The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, ESP8685 integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and baseband filters.

2.5.22.4 GHz Transmitter
The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of the power amplifier.
Additional calibrations are integrated to cancel any radio imperfections, such as:
•carrier leakage
•I/Q amplitude/phase matching
•baseband nonlinearities
•RF nonlinearities
•antenna matching
These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing.

2.5.3Clock Generator
The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators and dividers.
The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter.

2.5.4Wi­Fi Radio and Baseband
ESP8685 Wi-Fi radio and baseband support the following features:
•802.11b/g/n
•802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth
•802.11n MCS32
•802.11n 0.4 µs guard interval
•data rate up to 150 Mbps
•RX STBC (single spatial stream)
•adjustable transmitting power
•antenna diversity
ESP8685 supports antenna diversity with an external RF switch. This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.

2.5.5Wi­Fi MAC
ESP8685 implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled automatically with minimal host interaction to minimize the active duty period.
ESP8685 Wi-Fi MAC applies the following low-level protocol functions automatically:
•4 × virtual Wi-Fi interfaces
•infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode
•RTS protection, CTS protection, Immediate Block ACK
•fragmentation and defragmentation
•TX/RX A-MPDU, TX/RX A-MSDU
•transmit opportunity (TXOP)
•Wi-Fi multimedia (WMM)
•GCMP, CCMP, TKIP, WAPI, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise
•automatic beacon monitoring (hardware TSF)
•802.11mc FTM

2.5.6Networking Features
Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH networking, and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and 1.2 is also supported.

2.6Bluetooth LE
ESP8685 includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5 and Bluetooth mesh.

2.6.1Bluetooth LE Radio and PHY
Bluetooth Low Energy radio and PHY in ESP8685 support:
•1 Mbps PHY
•2 Mbps PHY for higher data rates
•coded PHY for longer range (125 Kbps and 500 Kbps)
•listen before talk (LBT), implemented in hardware
•antenna diversity with an external RF switch
This switch is controlled by one or more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.

2.6.2Bluetooth LE Link Layer Controller
Bluetooth Low Energy Link Layer Controller in ESP8685 supports:
•LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data
•multiple advertisement sets
•simultaneous advertising and scanning
•multiple connections in simultaneous central and peripheral roles
•adaptive frequency hopping and channel assessment
•LE channel selection algorithm #2
•connection parameter update
•high duty cycle non-connectable advertising
•LE privacy 1.2
•LE data packet length extension
•link layer extended scanner filter policies
•low duty cycle directed advertising
•link layer encryption
•LE Ping


2.7Low Power Management
With the use of advanced power-management technologies, ESP8685 can switch between different power modes:
•Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.
•Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wi-Fi base band, Bluetooth LE base band, and radio are disabled, but Wi-Fi and Bluetooth LE connection can remain active.
•Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip. Wi-Fi and Bluetooth LE connection can remain active.
•Deep-sleep mode: CPU and most peripherals are powered down. Only the RTC memory is powered on. Wi-Fi connection data are stored in the RTC memory.

For power consumption in different power modes, please refer to Table 14.


2.8Timers
2.8.1General Purpose Timers
ESP8685 is embedded with two 54-bit general-purpose timers, which are based on 16-bit prescalers and 54-bit auto-reload-capable up/down-timers.
The timers' features are summarized as follows:
•a 16-bit clock prescaler, from 1 to 65536
•a 54-bit time-base counter programmable to be incrementing or decrementing
•able to read real-time value of the time-base counter
•halting and resuming the time-base counter
•programmable alarm generation
•level interrupt generation

2.8.2System Timer
ESP8685 integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The system timer has the following features:
•counters with a fixed clock frequency of 16 MHz
•three types of independent interrupts generated according to alarm value
•two alarm modes: target mode and period mode
•52-bit target alarm value and 26-bit periodic alarm value
•automatic reload of counter value
•counters can be stalled if the CPU is stalled or in OCD mode

2.8.3Watchdog Timers
ESP8685 contains three watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT).
During the flash boot process, RWDT and the MWDT in timer group 0 (TIMG0) are enabled automatically in order to detect and recover from booting errors.
Watchdog timers have the following features:
•four stages, each with a programmable timeout value. Each stage can be configured, enabled and disabled separately
•interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or system reset for RWDT upon expiry of each stage
•32-bit expiry counter
•write protection, to prevent RWDT and MWDT configuration from being altered inadvertently
•flash boot protection
If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system.

2.9Cryptographic Hardware Accelerators
ESP8685 is equipped with hardware acneral algorithms, such as AES-128/AES-256 (FIPS PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), SHA1/SHA224/SHA256 (FIPS PUB 180-4), RSA3072, and
ECC. The chip also supports independent arithmetic, such as Big Integer Multiplication and Big Integer Modular Multiplication. The maximum operation length for RSA and Big Integer Modular Multiplication is 3072 bits. The maximum factor length for Big Integer Multiplication is 1536 bits.

2.10Physical Security Features
•Transparent external flash encryption (AES-XTS algorithm) with software inaccessible key prevents unauthorized readout of your application code or data.
•Secure boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can be booted.
•HMAC module can use a software inaccessible MAC key to generate MAC signatures for identity verification and other purposes.
•Digital Signature module can use a software inaccessible secure key to generate RSA signatures for identity verification.
•World Controller provides two running environments for software. All hardware and software resources are sorted to two groups, and placed in either secure or general world. The secure world cannot be accessed by hardware in the general world, thus establishing a security boundary.